Because of its increased radiation hardness and its use in nigh density, high performance commercial circuits, silicon on insulator (SOI) technology is currently being used in a variety of advanced integrated circuit applications. However, as device design rules continue to scale downwardly, the surface area occupied by (dielectric-filled) trenches which provide lateral isolation among the devices becomes an increasingly significant use of chip layout area. Another factor in the compactness achievable by a design layout entails first level interconnect and contact apertures. Typically, the interconnect structure involves the formation of apertures through a top surface layer of insulator material and an overlay or run (several microns or greater in length) of conductive material (e.g. metal) on the surface of the insulator between apertures. In addition, aperture size, aperture-to-aperture spacing, conductor overlap of the apertures and metal pitch rules combine to control the functional density for an entire device fabrication technology.